|
Article information
2016 , Volume 21, ¹ 6, p.104-112
Stempkovskiy A.L., Telpukhov D.V., Solovyev R.A., Myachikov M.V.
Methods for improvement of computing performance when calculating reliability metrics of combinational logic circuits
Purpose. The main objective of this work is to develop computational acceleration methods of fault-tolerance metrics evaluation for combinational circuits. The urgency of this goal stems from the fact that the computational complexity of direct methods for calculating fault tolerance characteristics of combinational circuits depends exponentially on the number of circuit inputs, making them unusable even for medium-sized schemes. Methodology. The paper presents a number of methods for increasing computing capacity when calculating reliability metrics for combinational logic circuits. Standard methods for optimization of calculations such as caching, caching with the changed order of calculation and vectorization underlie the proposed approaches to speed up computations due to more intensive use of memory. Findings. Within the framework of the research, it was found that highest efficiency, when working with the individual bit values, shows the single pass method of handling errors. Caching methods with a different order of input combinations, which consists of standard and Gray codes slightly differ due to a more complex Gray code input generation procedure for combinations. The most effective way to increase computing performance as a whole is vectorization: acceleration of computations was proportional to the used bit width. The disadvantage of this method is the requirement for the increased usage of memory. Originality/value. In this article, the practical methods for performance improvement in the calculation of reliability of combinational logic circuits have been considered. The high efficacy of the proposed acceleration methods has been empirically demonstrated on a broad set of tests
[full text]
Keywords: fault-tolerance, combinational circuit, sensitivity factor, caching
Author(s):
Stempkovskiy Alexander Leonidovich
Dr. , Academician RAS, Professor
Position: Director
Office: Institute for Design Problems in Microelectronis RAS
Address: 124365, Russia, Moscow
Phone Office: (499) 729-98-90
E-mail: stal09@ippm.ru
Telpukhov Dmitriy Vladimirovich
PhD.
Position: Research Scientist
Office: Institute for Design Problems in Microelectronics of Russian Academy of Sciences
Address: 124365, Russia, Moscow, 3, Sovetskaya Street
Phone Office: (499) 729-98-90
E-mail: dmtr@ippm.ru
Solovyev Roman Alexandrovich
PhD.
Position: Head of Departament
Office: Institute for Design Problems in Microelectronics of Russian Academy of Sciences
Address: 124365, Russia, Moscow, 3, Sovetskaya Street
Phone Office: (499) 729-98-90
E-mail: turbo@ippm.ru
Myachikov Mikhail Viktorovich
Position: engineer
Address: 124365, Russia, Moscow, 3, Sovetskaya Street
Phone Office: (499) 729-98-90
E-mail: myachikov92@gmail.com
References:
[1] Mahatme, N.N., Jagannathan, S., Loveless, T.D., Massengill, L.W., Bhuva, B.L., Wen, S.J. et al. Comparison of combinational and sequential error rates for a deep submicron process. IEEE Transactions on Nuclear Science (IEEE T NUCL SCI). 2011; 58(6):2719–2725.
[2] Dhillon, Y., Diril, A., Chatterjee, A. Soft-error tolerance analysis and optimization of nanometer circuits. Design, Automation and Test in Europe. Proceedings. 2005; (1):288–293.
[3] Mahatme, N.N., Gaspard, N.J., Assis, T., Jagannathan, S., Chatterjee, I., Loveless, T.D., Bhuva, B.L., Massengill, L.W., Wen, S.J., Wong, R. Impact of technology scaling on the combinational logic soft error rate. International Reliability Physics Symposium (IRPS). 2014: 5F.2.1–5F.2.6.
[4] Stempkovskiy, A.L., Telpukhov, D.V., Solovyev, R.A., Myachikov, M.V. Improving the Fault Tolerance of Logic Circuits Using Unconventional Majority Voters. Information Technologies. 2015; 21(10):749–756. (In Russ.)
[5] Stempkovskiy, A.L., Telpukhov, D.V., Solovyev, R.A., Myachikov, M.V., Telpukhova, N.V. The development of technology-independent metrics for evaluation of the masking properties of logic. Computational Technology. 2016. Vol. 21, No. 2. Ñ. 53–62. (In Russ.)
[6] von Neumann, J. Probabilistic logics and the synthesis of reliable organisms from unreliable components. Eds. C.E. Shannon and J. McCarthy. Automata Studies. Princeton, New Jersey: Princeton University Press; 1956: 43–98.
[7] Stempkovskiy, A.L., Telpukhov, D.V., Solovyev, R.A., Solovyev, A.N., Myachikov, M.V. Fault Simulation Technique for Logic Circuits Reliability Characteristics Evaluation. Information Technologies. 2014; (11):30–35. (In Russ.)
[8] Telpukhov, D.V., Solovyev, R.A., Myachikov, M.V. Development of practical metrics to evaluate the methods for increasing the fault tolerance of combinational circuits. Proceedings of the Intern. Scientific and Technical Conf. “Information Technologies and Mathematical Modeling of Systems 2015”. Moscow; 2015: 79–81. (In Russ.)
[9] Ibrahim W., Beiu V., Beg A. GREDA: A Fast and More Accurate Gate Reliability EDA Tool. IEEE Trans. Comput. Des. Integr. Circuits Syst. 2012; 31(4):509–521.
Bibliography link:
Stempkovskiy A.L., Telpukhov D.V., Solovyev R.A., Myachikov M.V. Methods for improvement of computing performance when calculating reliability metrics of combinational logic circuits // Computational technologies. 2016. V. 21. ¹ 6. P. 104-112
|
